1. Field of the Invention
This invention relates to the formation of a capacitor within integrated circuits and more particularly to capacitor structures that are immune to noise and unwanted signals for use in switched capacitor circuits.
2. Description of Related Art
The design and structure of capacitors within integrated circuits using standard CMOS processing is well understood in the art. Generally one of the plates, the bottom plate, is formed from the semiconductor substrate or is formed by a conductive layer of metal or polycrystalline silicon or polycide (a polycrystalline silicon layer covered with a layer of silicide) isolated from the substrate by an insulating layer of a material such a silicon dioxide and is directly coupled to the substrate through a parasitic capacitor. The parasitic capacitor often has a capacitance that is approximately equal to that of the designed capacitor.
When the designed capacitor is incorporated into an analog integrated circuit such as a switched capacitor filter, the impact of the parasitic capacitor must be accounted for in the design of the operating parameters of the analog integrated circuit.
Additionally, in integrated circuits combining analog and digital functions, noise and unwanted signals can be coupled from the digital circuits to the analog circuits causing improper operation of the analog circuits. The coupling of the noise and unwanted signals can be alleviated by proper placement or layout of the circuit components within the integrated circuits. In Analog MOS Integrated Circuits for Signal Processing, G. Temes & R. Gregorian, John Wiley & Sons, United States of America, 1986. In FIG. 7.43 on page 515, a power supply distribution and return circuit for the analog and digital circuits is shown. If the analog circuits share a common power supply distribution and return circuit with the digital circuits, the noise generated by such components of the digital circuitry as the digital clocking circuits, the simultaneous switching of the digital circuits, and the digital circuits rise and fall times will cause the power supply distribution and return circuit to couple this noise to the analog circuitry.
The power supply return circuit is often the substrate for the integrated circuits. With the noise and unwanted signals generated by the digital circuits present on the substrate, this noise will be coupled directly to the analog circuitry on the power supply distribution and return circuit. To avoid this problem, the power supply distribution and return circuits of the analog circuits are separated from those of the digital circuits.
However, just separating the power supply distribution and return circuits will not completely eliminate the coupling of the noise and unwanted signals coupled from the digital circuits to the analog circuits. The noise injected to the substrate from the power supply distribution and return circuit of the digital circuits will be coupled to the analog circuits directly through the designed capacitors if its bottom plate is the substrate, or through the parasitic capacitor, if the bottom plate is a conductive layer of metal, polycrystalline silicon, or polycide. Thus it has been recommended, such as in Temes and Gregorian at p. 517, that the bottom plate not be connected to the inverting input terminal of an op amp.
One technique to shield the design capacitor from the substrate, as shown in Temes and Gregorian, FIG. 7.47 page 518, by placing a diffusion of the opposite conductivity as the substrate between the design capacitor and the substrate. The diffusion is connected to the power supply reference voltage thus providing a low impedance path for any noise coupled from the substrate and avoiding the coupling to the analog circuit.
Other techniques, as shown in U.S. Pat. No. 5,220,483 (Scott), create a shielded top plate for the design capacitor and an unshielded bottom plate. The bottom plate will in fact be two layers of conductive material (one polycrystalline silicon and the other a second layer metal) connected together. The shielded top plate will be a first level of metal placed between the polycrystalline silicon and the second layer metal. Additionally, a second shielding layer of the first layer metal formed as a ring layer around the periphery of the top plate, will be connected to the power supply return circuit of the analog circuits.
As conventionally shown in the Scott patent, the shielded top plate will be placed in the analog circuits at nodes that would be sensitive to noise and the unshielded bottom plate at locations in the analog circuits that are insensitive to noise.
However, because the parasitic capacitor still exists, it now must be placed at locations restricted within the analog circuits. For example referring to the switched capacitor filter FIG. 5a, if capacitor CF1 were implemented as conventionally described, the shielded top plate would be connected to the inverting input--of the operational amplifier op amp.
The unshielded bottom plate would be placed at the output of the operational amplifier op amp thus placing the parasitic capacitor in parallel with the load capacitance Cl. The capacitive load on the output of the operational amplifier op amp will now be: ##EQU1## C.sub.eq is the equivalent load capacitance of the output of the operational amplifier.
C.sub.l is the actual load capacitance at the output of the operational amplifier. PA1 C.sub.f1 is the feedback capacitance of the operational amplifier. PA1 C.sub.i is the input capacitance of the operational amplifier. PA1 C.sub.p is the parasitic capacitance at the bottom plate of the capacitor C.sub.f1
Since the capacitance of the parasitic capacitor is approximately the same as that of the design capacitor, the parasitic capacitor can dramatically impact the performance of the switched capacitor filter.
U.S. Pat. No. 5,166,858 (Frake) shows a three layer capacitor having a first plate formed of a polycrystalline silicon conductor isolated from a substrate by an insulating layer. A second plate is formed of a first metal layer that is insulated form the first plate by a second insulating layer. A third plate is formed of a second metal layer and connected by a first metal connection to the first plate thus forming a "sandwich capacitor". The capacitor structure is for use in voltage doubling and voltage tripling applications on integrated circuits.
U.S. Pat. No. 5,589,416 (Chittipeddi) describes a method for the manufacture of an integrated circuit capacitor where the first plate of the capacitor is a polycrystalline silicon created during the processing of forming the gates of MOS Transistors. The second plate is formed of a Titanium Nitride upon a hard mask insulating layer. A second metal is in contact with the second plate of the capacitor to connect the capacitor to other circuitry of the integrated circuit.
U.S. Pat. No. 5,021,920 (Smith) describes a multilevel capacitor having interleaved capacitive plates of alternate conductivity types between layers of dielectric material. The layers of alternate conductivity types are connected together with one layer of one conductivity type at one connection and a second layer of the alternate conductivity type at the other connection. The alternate layers are isolated from each other by a biasing voltage attached to the connected layers. The layers of opposite conductivity types from the connecting layer form diodes preventing conduction of current through the diodes essentially isolating the layers from one another. This structure is suitable for dynamic random access memory.